This invention relates to a signal controlling method and apparatus.
A conventional signal dividing method for dividing (internally dividing or interpolating) a timing difference is used for multiplying the frequency of clock signals, as disclosed in Publication 1 (Japanese patent application 09-157028 (JP Patent Kokai JP-A-11-4145)).
In e.g., Publication 2 (ISSCC Digest of Technical Papers pp.216 to 217, February 1996, U.S. Pat. Nos. 5,442,835 and 5,530,837), there is disclosed a clock signal frequency multiplying circuit, as shown herein in FIG. 24.
Referring to FIG. 24, the clock signal frequency multiplying circuit is made up of four sets of delay circuits 301 to 304, a phase comparator 309 and a counter 310, in case of 4xc3x97 frequency multiplying.
Each of the first to fourth delay circuits 301 to 304 has its output terminals selected by first to fourth switchers 305 to 308, with the first to fourth delay circuits 301 to 304 being connected in series with one another.
A first clock 311, input from outside to the first delay circuit 301, is compared in the phase comparator 309 with a fifth clock 315 passed through the first to fourth delay circuits 301 to 304. An UP signal 316 or a DOWN signal 317 is transferred to the counter 310, based on the results of comparison, and a control signal 318 is output from the counter 310 to the first to fourth switchers 305 to 308 to make adjustment so that the first clock 311 will be of the same phase (in-phase) to the fifth clock 315.
Since the four delay circuits 301 to 304 are adjusted equally in delay time, the delay time is equal, with the timing difference of the first to fourth clocks 311 to 314 being equal to one another at one-fourth of the clock period tCK.
Thus, by synthesising the first to fourth clocks 311 to 314, 4xc3x97 clocks are produced.
As a circuit for multiplying the frequency of clock signals, a phase locked loop (PLL) is used. In the PLL, shown in FIG. 25, an output of a voltage-controlled oscillator VCO 322 is frequency-divided by a frequency divider 323, and the resulting signal is compared by a phase comparator 319 to an external clock 324. The result of comparison is input as an UP signal 325 or a DOWN signal 326 via a charging pump 320 and a loop filter 321 to the VCO322 to control the VCO 322 so that clocks obtained on frequency-dividing the output of the VCO 322 will be of a frequency equal to a frequency of the external clock 324. This causes the VCO 322 to output frequency-multiplied clocks 327 with the number of times of multiplying equal to a reciprocal of the number of times of frequency division.
However, the circuit shown in FIG. 24 is such a circuit comparing a signal which has traversed the series-connected delay circuits to external clocks approximately several tens of times to correct the delay difference and the phase difference progressively as comparison proceeds.
On the other hand, the PLL circuit, shown in FIG. 25, has a drawback that it is insufficient in operating speed, since clocks obtained on frequency division of the output of the VCO 322 will be of a frequency equal to the frequency of the external clock 324, such that a time interval not less than several tens of clock periods must elapse until the clocks multiplied in frequency are obtained.
The circuits shown in FIGS. 24 and 25 basically can be used only for clock control, while it cannot be used as a delay circuit for varying the degree of signal delay.
With a view to solving these drawbacks and to realizing a method and apparatus for controlling the clock signals also usable as a variable delay circuit, the present inventors have proposed the following circuit configuration in the JP-A-11-4145. The clock control circuit, described in JP-A-11-4145, is now explained by referring to the drawings, the entire disclosure of which is herein incorporated by reference thereto.
FIG. 4 shows the configuration of the JP-A-11-4145. The circuit shown in FIG. 4 multiplies the frequency of external clocks. Specifically, the circuit shown in FIG. 4 frequency divides external clocks 1 into multi-phase clocks 3 and divides the input timing difference of different phase pulse edges of the multi-phase clocks 3 or multiplexes the clocks 9c of different phases resulting from the division to multiply the phases of the external clock 1. The circuit shown in FIG. 4 includes a frequency divider 2, a multi-phase clock frequency multiplying circuit 5 and a clock synthesis circuit 8. The frequency divider 2 divides the frequency of the external clock 1 to the multi-phase clocks 3. A multi-phase clock multiplying circuit 5 includes a timing difference dividing circuit 4a for dividing pulses of different phases of different phase clocks of the multi-phase clocks 3, timing difference dividing circuits 4a for dividing the pulses of the same phase by n and a multiplying circuit 4b for multiplying different phase pulses resulting from division by n, and outputs multi-phase clocks 9a. 
The clock synthesis circuit 8 synthesises the multi-phase clocks 9a, output from the multiplying circuit 4b, to generate single-phase clocks 9. The timing difference dividing circuits 4a are connected in parallel with one another.
The external clocks 1 are frequency divided by the frequency divider 2 into the multi-phase clocks 3, and the input timing difference of different phase pulse edges of the frequency divided multi-phase clocks 3 is divided by a timing difference dividing circuit 4a. The resulting clocks 9c of different phases, obtained on frequency division, are multiplexed to multiply the external clock 1, to multiply the phases of the multi-phase clocks.
FIG. 5 shows an illustrative structure of a two-phase clock multiplying circuit as the multi-phase clock frequency multiplying circuit 5. The two-phase clock multiplying circuit divides the frequency of the external clocks 105 by two to output two-phase clocks having the double (2xc3x97) frequency.
In FIG. 5, a frequency divider 101 divides the frequency of the external clocks 105 by two to generate two-phase clocks D1, D2. Plural two-phase clock multiplying circuits 1021 to 102n divide the input timing difference of different phase pulse edges of the frequency divided multi-phase clocks D1, D2 (3 of FIG. 4), the first stage two-phase clock multiplying circuit 1021 generates two-phase clock signals D11, D12 obtained on frequency doubling the two-phase clocks D1, D2 from the frequency divider 101. In similar manner, the two-phase clock multiplying circuits 1021, 1023 to 102nxe2x88x921 each doubles the frequency of the clocks D21, D22 of the previous stage so that two-phase clocks Dn1, Dn2 obtained on 2nX-multiplying the external clocks 105 are obtained by the two phase clock multiplying circuit 102n of the last stage.
A clock synthesis circuit 103 synthesises 2nX-multiplied two-phase clocks Dn1, Dn2 output from the last stage two phase clock multiplying circuit 102n to output multiplied clocks 107.
A period detection circuit 104 (6 of FIG. 4) is fed as an input with the external clocks 105 to output a control signal 106 (7 of FIG. 4) to each two-phase clock multiplying circuits 1021 to 102n. The control signal 106 corrects the clock period dependency of the timing difference dividing circuit contained in each two-phase clock multiplying circuits 1021 to 102n for load adjustment.
The period detection circuit 104 is made up of a ring oscillator of a fixed number of stages and counters and counts the number of oscillations of the ring oscillators during the period of the external clocks 105 to output a control signal 105 depending on the number of counts.
The two-phase clock multiplying circuits 1021 to 102n are freed of fluctuations in characteristics by the control signal 106 from the period detection circuit 104.
The circuit shown in FIG. 5 divides the frequency of the external clocks 105 by a xc2xd frequency divider 101 and doubles the frequency of the clocks D1, D2 by the initial state two-phase clock multiplying circuit 1021 to generate two-phase clocks D11, D12. The similar process is repeatedly carried out in the two-phase clock multiplying circuits 1022 to 102n until 2nX two-phase clocks Dn1, Dn2 are ultimately obtained from the last stage two-phase clock multiplying circuits 102n.
These clocks Dn1, Dn2 are synthesised by the clock synthesis circuit 103 to produce multiplied clocks 107.
In the embodiment shown in FIG. 6, in which n=4, the multiplied clocks 107 are of the same clock period as that of the external clocks 105 and are obtained as signals 2nX (8X) from the external clocks 105. Meanwhile, n=4 is merely illustrative such that n may be set to any suitable integer.
FIG. 7 shows a structure of the two-phase clock multiplying circuit 5. Since the two-phase clock multiplying circuits 1021 to 102n are of the same structure, the following explanation is directed to the last stage two-phase clock multiplying circuits 102n. The structure of the two-phase clock multiplying circuits 102n is designed for the setting of n=4.
The two-phase clock multiplying circuit 102n includes parallel-connected first to fourth timing difference dividing circuits 108 to 111 and first and second multiplexing circuits 112, 113. Two phase clocks D (nxe2x88x921) 1, D (nxe2x88x921) 2 are input to two input ends of the first to fourth timing difference dividing circuits 108 to 111. The control signal 106 and four phase clocks P1 to P4 from the timing difference dividing circuits 108 to 111 in the complementary configuration are fed back to the input side.
The first and second multiplexing circuits 112, 113 are fed with and multiplex two-phase clocks P1, P3 and P2, P4 from the first to fourth timing difference dividing circuits 108 to 111 to generate two-phase clocks Dn1, Dn2.
The operation of the two-phase clock multiplying circuit, shown in FIG. 7, is explained with reference to FIG. 8.
The two-phase clock multiplying circuit 102n is fed with two-phase clocks D (nxe2x88x921) 1 and D (nxe2x88x921) 2 from the previous stage and with the control signal 106 from the period detection circuit 104 to output frequency doubled two-phase clocks Dn1, Dn2.
In the two-phase clock multiplying circuit 102n, the two-phase clocks D (nxe2x88x921) 1 and D (nxe2x88x921) 2 and the control signal 106 are input to the totality of the four timing difference dividing circuits 108 to 111. The clocks P1 to P4 are output from the four timing difference dividing circuits 108 to 111 so as to be fed back as inputs to the associated timing difference dividing circuits 108 to 111.
Referring to FIG. 8, the rising of the clock P1 is determined by the delay corresponding to the inner time delay of the timing difference dividing circuit 108 as from the rising of the clock D (nxe2x88x921) 1.
The rising of the clock P2 is determined by the division of the timing difference between the rising of the clock D (nxe2x88x921) 1 and that of the two-phase clock D (nxe2x88x921) 2 and the delay corresponding to the internal delay.
The rising of the clock P3 is determined by the delay corresponding to the internal delay as from the clock D (nxe2x88x921) 2. The rising of the clock P4 is determined by the division of the timing difference between the rising of the clock D (nxe2x88x921) 2 and that of the clock D (nxe2x88x921) 1 and the delay corresponding to the internal delay as from the clock D (nxe2x88x921) 2.
The clock P2 controls the decay (falling) of the clock P1 input to the timing difference dividing circuit 108. The clock P3 controls the decay of the clock P2 input to the timing difference dividing circuit 109. The clock P4 controls the decay of the clock P3 input to the timing difference dividing circuit 110. The clock P1 controls the decay of the clock P4 input to the timing difference dividing circuit 111.
So, the periods of the clocks P1 to P4 are equal to those of the clocks D (nxe2x88x921) 1 and D (nxe2x88x921) 2 such that the clocks P1 to P4 become substantially four-phase signals with a 25% duty.
Moreover, the clocks P1, P3 are input to and multiplexed by the multiplexing circuit 112 so as to be output as a clock signal Dn1.
The clocks P2, P4 are input to and multiplexed by the multiplexing circuit 113 so as to be output as a clock signal Dn2.
The clocks Dn1, Dn2 are two-phase clocks with subsequently 50% duty, with the periods thereof being one-half those of the clocks D (nxe2x88x921) 1 and D (nxe2x88x921) 2.
Referring to FIGS. 9 to 12, typical structures of the timing difference dividing circuits 108 to 111, shown in FIG. 7, are explained. In FIGS. 9 to 12, MP11, MP21, MP31 and MP41 are P-channel MOS transistors, MN11 to MN19, MN21 to MN29, MN31 to MN39 and MN41 to MN49 are N-channel MOS transistors, while CAP11 to CAP 13, CAP21 to CAP23, CAP31 to CAP33 and CAP41 to CAP43 are capacitance devices.
The timing difference dividing circuits 108 to 111 are of the identical device structure. That is, each of the difference dividing circuits 108 to 111 is made up of a two-input NAND 10, an inverter 11, a sole P-channel MOS transistor MP11 etc., three sets each of two-series connected N-channel MOS transistors, three sets each of a series-connected N-channel MOS transistor and a capacitance device. The three NAND transistors are all of an identical gate width, with the gate width of the three sets of NMOS transistors and the capacitance of the capacitance device being of a size ratio of 1:2:4.
The difference dividing circuits 108 to 111, shown in FIGS. 9 and 11, are similar in structure, with the difference being the connection of inputs D (nxe2x88x921) 1 and D (nxe2x88x922) 2 and the connection of the input P2 (P4).
Referring to FIG. 9, the timing difference division circuit 108 includes a NAND circuit NAND11, having a signal D (nxe2x88x921) 2 and a signal P2 as inputs, a P-channel MOS transistor MP11 having a source, a gate and a drain connected to a power source VCC, to an output end (node 11) of the NAND11 and to an internal node N12, respectively, N-channel MOS transistors MN12, MN13 each having a drain and a gate connected to the inner node N12 and to a signal D (nxe2x88x921) 1, respectively, a N-channel MOS transistor MN11 having a gate connected to ground potential, and N-channel MOS transistors MN14, MN15 and MN16, having sources commonly connected to the ground potential GND and gates commonly connected to an output end of NAD 11. The inner node N12 is connected to an input end of an inverter INV11 to output a signal P1 at an output terminal of the inverter INV11. The inner node N12 is provided with N-channel MOS transistors MN17, MN18 and MN19, having drains commonly connected and having gates connected to a control signal 106, and with capacitances CAP11, CAP12 and CAP13, having one end connected to a source of N-channel MOS transistors MN17, MN18 and MN19 and having the other ends commonly connected to the ground potential.
Referring to FIG. 10, a timing differential circuit 109 include a NAND circuit NAND 21, fed with a signal D (nxe2x88x921) 2 and with a signal P3 as inputs, a P-channel MOS transistor MP21, having a source, a gate and a drain connected to the power source VCC, to an output end (node N21) of the NAND21 and to the inner node N22, respectively, an N-channel MOS transistor MN21 having a drain and a gate connected to the inner node N22 and to the signal D (nxe2x88x921) 1, respectively, N-channel MOS transistors MN22 and MN23, having drains and gates connected commonly to the inner node N22 and to the signal D(nxe2x88x921)2, respectively, and N-channel MOS transistors MN24, MN25 and MN26 having sources commonly connected to the ground potential GND and gates commonly connected to an output end (node N21) of the NAND21. The inner node N22 is connected to the input end of the inverter INV21 to output a signal P3 at an output end of the inverter INV21. The inner node N22 includes N-channel MOS transistors MN27, MN28 and MN29 having drains commonly connected and having gates connected to a control signal 106, and capacitances CAP21, CAP22 and CAP23 having one ends connected to sources of N-channel MOS transistors MN27, Mn28 and MN29 and having the other ends commonly connected to the ground potential.
Referring to FIG. 11, a timing difference division circuit 110 includes a NAND circuit NAND31, fed with the signal D (nxe2x88x921) 1 and with a signal P4, as input, a P-channel MOS transistor MP31 having a source, a gate and a drain connected to the power source VCC, to an output end of the NAND31 and to an inner node N32, respectively, N-channel transistors MN32, MN33, having drains commonly connected to the inner node N32 and having gates commonly connected to the signal D (nxe2x88x921) 2, a N-channel MOS transistor MN31 having a gate connected to the ground potential, and N-channel MOS transistors Mn34, MN35 and MN36 having sources commonly connected to the ground potential GND and having gates commonly connected to the output end of the NAND31. The inner node N32 is connected to the input end of the inverter INV31 and outputs a signal P3 at an output end of the inverter INV31. The inner node N32 includes N-channel MOS transistors MN37, MN38 and MN39 having drains commonly connected and having gates connected to control signals, and capacitances CAP31, CAP32 and CAP33 having one ends to sources of N-channel MOS transistors MN37, MN38 and Mn39 and having the other ends commonly connected to the ground potential.
Referring to FIG. 12, a timing difference division circuit 111 includes a NAND circuit NAND41, fed with the signal D (nxe2x88x921) 1 and with the signal P1, a P-channel MOS transistor MP41 having a source, a drain and a gate connected to the power source VCC, to an output end (node N41) of the NAND41 and to an inner node N42, respectively, an N-channel MOS transistor MN41 having a drain and a gate connected to the internal node N42 and to the signal D (nxe2x88x921) 2, N-channel MOS transistors MN42, MN43 having drains and gates commonly connected to the inner node N42 and connected to the signal D(nxe2x88x921)1, respectively, and N-channel MOS transistors MN44, MN45 and MN46 having sources and gates commonly connected to the ground potential GND and commonly connected to an output end of the NAND41, respectively. The inner node N41 is connected to an input end of the inverter INV41 and outputs a signal P4 at an output end of the inverter INV41. The inner node N42 includes N-channel MOS transistors MN47, MN48 and MN49, having drains commonly connected and also having gates connected to a control signal, and capacitances CAP41, CAP42 and CAP43, having one ends connected to the sources of the N-channel MOS transistors MN47, MN48 and MN49 and having the other ends commonly connected to the ground potential.
The operation of the timing difference division circuits 108 to 111 is explained by referring to the timing waveform diagram of FIG. 13. The timing difference division circuits 108, 110, shown in FIGS. 9 and 11, are of the same circuit configuration except input/output signal, while the timing difference division circuits 109, 111 shown in FIGS. 10 and 12 are of the same circuit configuration except the input/output signals. So, the operation of the timing difference division circuits 108, 109, shown in FIGS. 9 and 10 are hereinafter explained.
As for the inner operation of the timing difference division circuit 108, shown in FIG. 9, one period is from t1 until t3 in FIG. 13. So, the inner node waveform for this one period duration is shown.
First, the rise timing of the clocks P1 is explained.
By a rising edge of a clock D (nxe2x88x921) 1, electrical charges at the node N12 are extracted to the N-channel MOS transistors MN12, MN13. When the potential of the node N12 has reached a threshold value of the inverter INV11, there rises an edge of the clock P1, output from the inverter INV11.
If the electrical charges of the internal node N12 that need to be extracted until reaching the threshold value of the inverter INV11 are denoted CV and charge-extracting current values of the N-channel MOS transistors MN12 and MN13 are denoted I, the result of extraction of the electrical charges of CV from the clock D (nxe2x88x921) 1 with the current of 2I, that is CV/2I, represents the timing as from the rising edge of the clock D (nxe2x88x921) 1 until rising of the clock P1.
The decay of clocks P1 is by the output of the two-input NAND 11 going low to turn ON the P-channel MOS transistor MP11 to charge the inner node N12 to a high level. The two-input NAND 11 is fed with a clock D (nxe2x88x921) 2 and a clock P2, with the output going low when both the clock D (nxe2x88x921) 2 and the clock P2 are high. The period during which the clock P2 is high is comprised within a period during which the clock D (nxe2x88x921) 2 is high, so that the output clock is of a pattern corresponding to a pattern of the inverted clock P2. However, during the time an initial value of the clock P2 is not fixed with the power being turned on, a logical value is taken of the clock P2 and the clock D (nxe2x88x921) 2.
As for the operation of the timing difference division circuit 109, shown in FIG. 10, there is shown the internal node waveform during the time period as from t1 until t3 in FIG. 13, because this time period corresponds to one period.
The rise timing of the clock P2 is explained. During the time period tCKn as from the rising edge of the clock D (nxe2x88x921) 1, the electrical charges of the node N22 are extracted by the N-channel MOS transistor MN21. After time tCKn, the residual electrical charges at the node N22 are extracted from the rising edge of the clock D (nxe2x88x921) 2 by the N-channel MOS transistors MN22, MN23. When the potential of the node N22 reaches the threshold value of the inverter INV21, the edge of the clock P2 rises. If the electrical charges of the node N22 are denoted CV, and the charge extracting current values of the N-channel MOS transistors MN22, MN23 are denoted I, the result of extracting the current CV from the clock D (nxe2x88x921) 1 during the time period tCKn with the current I, and during the remaining period with 2I, that is
tCKn+(CVxe2x88x92tCKxc2x7I)/2I=CV+tCKn/2
represents the timing as from the rising edge of the clock D(nxe2x88x921) 1 until the rising of the clock P2.
Therefore, the timing difference with respect to the rising of the clock P1 is just equal to tCKn/2.
The decay timing of the clock P2 is caused by an output of the two-input NAND 21 going low to turn the P-channel MOS transistor MP21 on to charge the node N22 to high. The output of the two-input NAND 21 goes low only when a clock D (nxe2x88x921) 2 and a clock P3 are fed as inputs and both the clock D (nxe2x88x921) 2 and the clock P3 are high.
The clocks P3 and P4 are now explained. Since the timing difference between the rising edge of the clock D (nxe2x88x921) 1 and that of the clock D (nxe2x88x921) 2 is tCKn, the rise timing difference between the clocks P1 and P3 is tCKn. So, the rising timing difference between the clocks P2 and P3 is also xc2xdtCKn. Similarly, the rising timing difference between clocks P3 and P4 and that between clocks P4 and P1 are also xc2xdtCKn.
Therefore, the clocks P1 to P4 are four-phase signals of 25% duty, as mentioned previously.
The clocks P1 and P3 and the clocks P2 and P4 are respectively multiplexed by multiplexing circuits 112, 113, each being comprised of a NOR circuit NOR12 and an inverter INV13, shown in FIG. 14, and become two-phase clock signals of 50% duty.
In order for the rising of the clock P2 to be xc2xdtCKn for the rising of the clock P1, the condition that the threshold value of the inverter INV21 be not reached even when electrical charges of the node N22 are extracted by the N-channel MOS transistor MN21 during the period of tCKn, that is the condition of
CVxe2x88x92tCKnxc2x7I greater than 0
need to be met.
However, tCKn is not previously determined by the period of the external clock 1 at the time of designing, so that the current I is fluctuated with device characteristics.
Therefore, in order to cope with this, the CV value is varied depending on the period of the external clock 105 and with device characteristics.
The gates of the N-channel MOS transistors, connected to the capacitance device (MN17 to MN19 in FIG. 9), are fed with a control signal 106, as explained previously, such that the load of the common node N12 can be varied with the control signal 106.
Since the N-channel MOS transistors and the capacitance devices are set to the size ratio of 1:2:4, eight-stage adjustment is possible.
The control signal 106 is a value corresponding to the count value of the number of times of oscillations of the ring oscillator, obtained by a counter, during a period of the external clock 105, in a period detection circuit 104. In this circuit configuration, since the relation between the period of the external clocks and the period of the ring oscillator representative of device characteristics is coded, not only is the operating range not increased relative to the period of the external clocks 1, but also variations in the device characteristics are resolved.
In the present conventional structure, two-phase clock multiplying circuits 1021 to 102n are connected in series, with the frequency of the respective input clocks D1, D to D (nxe2x88x921) 1 and D (nxe2x88x921) 2 increasing at a factor of two, so that the capacitance value is adjusted between the two-phase clock multiplying circuits 1021 to 102n in order to optimise the CV value.
In the conventional circuit, described above, multiplied clocks can be generated by dividing the frequency of the external clocks 1 by two to generate two-phase clocks without using feedback circuits, such as PLL or DLL.
FIG. 15 shows a circuit configuration explained as the second embodiment in the JP-A-11-4145 and including a xc2xc frequency divider 201, series-connected four-phase clock multiplying circuits 2021 to 202n, a clock synthesis circuit 203 and a period detection circuit 204.
The operation of the circuit shown in FIG. 15 is explained with reference to the timing diagram of FIG. 16. This circuit divides the external clock signals 205 by the xc2xc frequency divider 201 to generate four-phase clocks Q1 to Q4 which are frequency-doubled by a four-phase clock multiplying circuit 202, to generate four-phase clocks Q11 to Q14. The similar process is repeated up to four-phase clock multiplying circuits 2021 to 202n to generate four-phase clocks Q1 to Q4 frequency multiplied by a factor of 2n. These clocks are synthesised by a clock synthesis circuit 203 to generate multiplied clocks 207.
The period detection circuit 204 is made up of a fixed number of steps of ring oscillators and counters. Specifically, the number of times of oscillations of the ring oscillator during the period of the external clocks 205 is counted by a counter, and a control signal 206 is generated depending on the count value to adjust the load in the four-phase clock multiplying circuits 2021 to 202n. By the period detection circuit 204, the operating range of the external clocks of the circuit and variations in the device characteristics may be resolved.
Referring to FIG. 17, the structure of the four-phase clock multiplying circuit 202 is explained. The four-phase clock multiplying circuits 2021 to 202n are of the same configuration. Referring to FIG. 17, the four-phase clock multiplying circuit 202n is made up of eight timing difference division circuits 208 to 215, eight pulse width correction circuits 216 to 223 and four multiplexing circuits 224 to 227.
The inner structures of the eight timing difference division circuits 208 to 215, eight pulse width correction circuits 216 to 223 and four multiplexing circuits 224 to 227 will be explained subsequently.
Referring to FIGS. 17 and 18, the internal connection and operation of the four-phase clock multiplying circuit 202n are hereinafter explained. The four-phase clock multiplying circuit 202, is fed with four-phase clocks Q (nxe2x88x921) 1 to Q (nxe2x88x921) 4 and a control signal 206 from the period detection circuit 204 to output frequency doubled four-phase clocks Qn1 to Qn4.
In the four-phase clock multiplying circuit 202,, the control signal 206 is input to the eight timing difference division circuits 208 to 215. The clocks Q (nxe2x88x921) to D (nxe2x88x921) 4 are input to the timing difference division circuits 208, 210, 212, 214, one signal at a time, while being input to the timing difference division circuits 209, 211, 213, 215, two signals at a time. Eight clocks T21 to T28 are output from the eight timing difference division circuits 208 to 215.
The rising of the clocks T21 is determined by the delay corresponding to the internal delay as from the rising of the clock Q (nxe2x88x921) 1.
The rising of the clock T22 is determined by the timing division of the rising of the clock Q (nxe2x88x921) 1 and the rising of the clock Q (nxe2x88x921) 2 and by the inner delay.
The rising of the clock T23 is determined by the delay corresponding to the inner delay as from the rising of the clock Q (nxe2x88x921) 2.
The rising of the clock T24 is determined by the timing division of the rising of the clock Q (nxe2x88x921) 2 and the rising of the clock Q (nxe2x88x921) 3 and by the inner delay.
The rising of the clock T25 is determined by the delay corresponding to the inner delay as from the rising of the clock Q (nxe2x88x921) 3.
The rising of the clock T26 is determined by the timing division of the rising of the clock Q (nxe2x88x921) 3 and the rising of the clock Q (nxe2x88x921) 4 and by the inner delay.
The rising of the clock T27 is determined by the delay corresponding to the inner delay as from the rising of the clock Q (nxe2x88x921) 4.
The rising of the clock T28 is determined by the timing division of the rising of the clock Q (nxe2x88x921) 4 and the rising of the clock Q (nxe2x88x921) 1 and by the inner delay.
The clocks T21 and T23 are input to a pulse width correction circuit 216 which then outputs an L pulse P21 having a decaying edge determined by the clock T21 and a rising edge determined by the clock T23. By a similar sequence of operations, pulses p22 to P28 are generated. So, the clocks P21 to P28 are eight pulses with 25% duty respectively dephased by 45xc2x0.
The clocks P25, dephased by 180xc2x0 from the clock P21, are multiplexed and inverted by the multiplexing circuit 224 and output as 25%-duty clock Qn1. In a similar sequence of operations, clocks Qn2 to Qn4 are generated. So, the clocks Qn1 to Qn4 are 50%-duty four-phase H pulses each with a dephasing of 90xc2x0.
The period of the clocks Qn1 to Qn4 is just one-half that of the clock Q (nxe2x88x921) 1 to Q (nxe2x88x921) 4. That is, the clock frequency is doubled in the course of generating the clocks Qn1 to Qn4 from the clocks Q (nxe2x88x921) 1 to Q (nxe2x88x921) 4.
Referring to FIGS. 19 and 20, the circuit configuration of the timing difference division circuits 208 to 215 is explained. The timing difference division circuits 208 to 215 are of the same circuit configuration.
In the following, only the timing difference division circuits 208 and 209 are explained. FIGS. 19 and 20 show the circuit configuration of the timing difference division circuits 208 and 209, respectively. The circuits shown in FIGS. 19 and 20 are similar in structure except that the two inputs vary. That is, the input signals to the two-input NOR circuit differ in FIGS. 19 and 20.
The timing difference division circuit 208 has an inner node N51, as an output node of the two-input NOR 51, having the same input Q (nxe2x88x921) 1 as an input. The inner node N51 is connected to an input end of the inverter INV51, which outputs T21 at its output end. The timing difference division circuit 208 also includes N-channel MOS transistors MN51, MN52 and MN53, having drains commonly connected to the inner node N51, and which are controlled on and off by a control signal 206 from the period detection circuit 204 being coupled to the gates, and capacitances CAP51, CAP52 and CAP53 connected across the sources of the N-channel MOS transistors MN51, MN52 and MN53 and the ground potential. The gate widths of the N-channel MOS transistors MN51, MN52 and MN53 and the capacitances CAP51, CAP52 and CAP53 are set to the size ratio of e.g., 1:2:4. The clock period is set by eight-stage adjustment of the load connected to the common node based on the control signal 206 output from the period detection circuit 204.
The timing difference division circuit 209 has an inner node N61, as an output node of the two-input NOR 61, having the same input Q (nxe2x88x921) 2 as an input. The inner node N61 is connected to an input end of the inverter INV61, which outputs T22 at its output end. The timing difference division circuit 208 also includes N-channel MOS transistors MN61, MN62 and MN63, having drains commonly connected to the inner node N61, and which are controlled on and off by a control signal 206 from the period detection circuit 204 being coupled to the gates, and capacitances CAP61, CAP62 and CAP63 connected across the sources of the N-channel MOS transistors MN61, MN62 and MN63 and the ground potential. The gate widths of the N-channel MOS transistors MN61, MN62 and MN63 and the capacitances CAP61, CAP62 and CAP63 are set to the size ratio of e.g., 1:2:4. The clock period is set by eight-stage adjustment of the load connected to the common node based on the control signal 206 output from the period detection circuit 204.
The operation of the timing difference division circuits 208, 209 is now explained by referring to the timing waveform shown in FIG. 21.
The operation of the timing difference division circuit 208 is finished during the time period from tc21 until tc24 of FIG. 21. So, the waveform of the inner node N51 during this time period is shown.
First, the rising timing of the output clock T21 is explained. The two-input NOR 51 includes two P-channel MOS transistors for connecting input signals IN1, IN2 to the gates, and two N-channel MOS transistors, connected in parallel across the output end and the ground and having gates fed with the input signals IN1, IN2.
When the electrical charges of the node N51 are extracted by the NOR51 with the rising edge of the clock Q (nxe2x88x921) 1, so that the potential of the node N22 reaches the threshold value of the inverter INV51, the edge of the clock T21, output by the inverter INV51, rises. If the electrical charges of the node N51 that need to be extracted until the threshold value of the inverter INV51 is reached, are denoted CV, and the charge extracting current values of the N-channel MOS transistors are denoted I, the result of extracting the electrical charges CV from the rising of the clock Q (nxe2x88x921) 1, that is CV/2I, represents the timing from the rising of the clock Q (nxe2x88x921) until rising of the clock T21.
The rising of the clock T21 is by the clock Q (nxe2x88x921) 1 going low to charge the output node N51 of the two-input NOR51 to high.
As for the operation of the timing difference division circuit 209, shown in FIG. 20, the operation of the timing difference division circuit 209 is well-nigh finished during the time period from ta21 until ta24 of FIG. 21. So, the waveform of the inner node N61 during this time period is shown.
First, the rising timing of the output clock T22 is explained. During the time period tCKn as from the rising edge of the clock D (nxe2x88x921) 1, the electrical charges of the inner node N22 are extracted by the N-channel MOS transistor. After time tCKn, the residual electrical charges at the inner node N61 are extracted from the rising edge of the clock Q (nxe2x88x921) 2 by the N-channel MOS transistors, so that, when the potential of the node N61 reaches the threshold value of the inverter INV61, the edge of the clock T22 rises. If the electrical charges of the node N61 are denoted CV, and the charge extracting current values of the N-channel MOS transistors of the two-input NOR61 are denoted I, the result of extracting the current CV from the clock Q (nxe2x88x921) 1 during the time period I of tCKn with the current I, and during the remaining period with 2I, that is
tCKn+(CVxe2x88x92tCKnxc2x7)/2I=CV+tCKn/2
represents the timing as from the rising edge of the clock Q(nxe2x88x921) until the rising of the clock T22.
Therefore, the timing difference with respect to the rising of the clock T21 is just equal to tCKn/2.
The rising of the clock T22 is by both the clocks Q (nxe2x88x921) 1 and clocks Q (nxe2x88x921) 12 going low to charge the output node N61 of the two-input NOR61 high.
The same explanations apply for clocks T23 to T28, that is, the rise timing differences of the clocks T21 to T28 are respectively equal to xc2xdtCKn.
The pulse width correction circuits 216 to 223 are each made up of an inverter INV71 and a two-input NAND 71, as shown in FIG. 22, and generate eight-phase pulses (split signals) P21 to P28, with the duty of 25%, with a dephasing being 45xc2x0.
The multiplexing circuit 224 is comprised of a two-input NAND 81, and generates 50% duty four-phase clocks Qn1 to Qn4, having a dephasing of 90xc2x0, as mentioned previously. The period of the clocks Qn1 to Qn4 is just one-half the clock Q (nxe2x88x921) 1 to Q (nxe2x88x921) 4.
In the present conventional clock multiplying circuits, the condition required to make the load of the common node N61 variable is the same as that in FIG. 9. So, the capacitances and NMOS transistors having the same operating object are used in combination. It is possible not only to increase the operating range for the period of the external clock signals 205 but also to eliminate variations in device characteristics.
In the above-described conventional multiplying circuit, proposed in the JP-A-11-4145, multiplied clocks may be produced by frequency-dividing the external clocks by a factor of four to prepare four-phase clocks at the outset, without using feedback circuits, such as PLL or DLL.
There may also be derived an advantage that, by frequency division by a factor of four, multiplying circuits may be constructed by fully static simple circuits using basic CMOS devices, such as NAND, NOR or inverters.
In the JP-A-11-4145, two-phase multiplied clocks are generated from two-phase clocks, while four-phase multiplied clocks are generated from four-phase clocks. It is however possible to connect plural timing difference division circuits in parallel in a tree-like fashion to increase the number of clock phases exponentially to 2, 4 or 8 to generate higher frequency components.
In the JP-A-11-4145, multiplied clocks may be generated extremely readily by frequency dividing external clocks into multi-phase clocks and taking an intermediate timing of each phase without the necessity of using a loop configuration.
So, the time period in which to produce multiplied clocks may be shorter, while the number of required clocks can be predicted at the outset, and hence the queuing time until using the multiplied clocks may be reduced appreciably.
The method of realising multiples other than powers of two by a similar technique is described in JP Patent Application 09-157042 (JP-A-11-4146), the entire disclosure thereof being herein incorporated by reference thereto.
However, in the timing difference division circuit (interpolator) in the multiplying circuits, as proposed in JP-A-11-4146 and in JP-A-11-4145, since multi-phase clocks are directly input as input signals, the operating range is not enlarged to the maximum extent.
For example, if the capacitance value of the capacitance device is fixed and four-phase clock signals are input, there is a constraint that the capacitance value which is just one half of the input phase difference is in a range from 1:3 for the smallest and largest values, as now explained.
FIG. 26 shows an illustrative structure of a conventional timing difference division circuit. Referring to FIG. 26, the conventional timing difference division circuit includes a logical sum circuit OR1, fed with first and second input signals IN1, IN2, a P-channel MOS transistor MP1, connected across the power source VCC and the inner node N26 and to the gate of which an output signal of the logical sum circuit OR1 is fed, an inverter INV3, for outputting an inverted version of the potential of the inner node N26, and N-channel MOS transistors MN1, MN2, each having a drain connected to the inner node N26, a gate fed with first and second input signals IN1, IN2, respectively, and a source connected to a constant current source 10. Across the inner node N26 and the ground are connected switching devices MN11 to MN15, comprised of N-channel MOS transistors, and capacitances CAP11 to CAP15. As in the timing difference division circuit, explained with reference to FIGS. 9 to 12, a control signal 106 output from the period detection circuit is connected to control terminals (gate terminals) of the switching devices MN11 to MN15, comprised of N-channel MOS transistors, to set a capacitance value to be appended to the inner node N26.
When the first and second input signals IN1, IN2 are of low levels, an output of the logical sum circuit OR1 goes low to turn on the P-channel MOS transistor MP1 to charge the inner node N26 to the power source potential so that the output of the inverter INV3 goes low.
When one or both of the first and second input signals IN1, IN2 are high, an output of the logical circuit OR1 goes high to turn the P-channel MOS transistor MP1 and the power source path of the inner node N26 and the power source VCC off, while one or both of the N-channel MOS transistors MN1 and MN2 are on, to discharge the inner node N26. When the potential of the inner node N26 starts to be decreased from the power source potential, until a potential that is not higher than the threshold value of the inverter INV3, an output of the inverter INV3 starts from the low level to the high level.
FIG. 27 illustrates the operation of the timing difference division circuit (TMD). Referring to FIG. 27a, two outputs of the first timing difference division circuit (TMD) of the three timing difference division circuits are fed with the same input signal IN1 to output an output signal OUT1. The second timing difference division circuit (TMD) is fed with the input signals IN1, IN2 to output an output signal OUT2, while the third timing difference division circuit (TMD) is fed at two inputs thereof with the same input signal IN2 to output an output signal OUT3. Of these, the second timing difference division circuit (TMD) fed with the input signals IN1, IN2 to output the output signal OUT2 is matched to the structure of the timing difference division circuit 209 of FIG. 17. On the other hand, the timing difference division circuit (TMD) commonly fed with IN1 and the timing difference division circuit (TMD) commonly fed with IN2 are configured for being fed with the same signal in FIG. 26 and hence is matched to the configuration of the timing difference division circuit 208 of FIG. 17.
FIG. 27b shows outputs OUT1 to OUT3 of the first to third timing difference division circuits fed with input signals IN1, IN2 of the timing difference T and changes A1 to A3 of the inner nodes of the first to third timing difference division circuits. For facilitating the description, it is assumed that the inner node is charged from the zero potential and, when the threshold value Vt is exceeded, the output signal is changed from the low level to the high level.
Referring to FIG. 27b, there is a timing difference between the input signals IN1 and IN2, the first timing difference division circuit (TMD) issues an output signal OUT1 with a delay time t1, the third timing difference division circuit (TMD) issues an output signal OUT3 with a delay time t3 and the second timing difference division circuit (TMD) issues an output signal OUT2 with a delay time t2, with the delay time t2 being of a value corresponding to the interior division of the delay time t1 and the delay time t3, such that
T1=CV/2I
t2=T+(CVxe2x88x92IT)/(2I)=T/2+CV/2I.
On the other hand, t3=T+CV/2I. It is noted that electrical charges discharged until the threshold value of the buffer circuit (inverter), to the input end of which is connected the inner node, is exceeded, is denoted CV.
FIG. 28 is a signal waveform diagram showing, for two-phase clocks IN1, IN2 obtained on frequency division of the clocks with the period equal to tCK, the manner of voltage changes in the inner node 26 and input signals in case the in-phase signals and phase signals are input to the timing difference division circuit shown in FIG. 26.
Referring to FIGS. 26 and 28, if electrical charges discharged until the threshold value of the inverter INV3 is exceeded are CV, where C is a capacitance value appended to the inner node N26, and V is the threshold voltage t of the inverter INV3, the N-channel MOS transistors MN1, MN2 are turned on, in case of the in-phase input, by the rising of the input signal IN1 from the low level to the high level, to turn the N-channel MOS transistors MN1, MN2 on to discharge the electrical charges with the current 2I. The time period during which the N-channel MOS transistors MN1, MN2 are turned on is not longer than 2tCK, so that, if the electrical charges are not extracted during 2tCK, there is produced no output at an output end of the timing difference division circuit.
So, the capacitance value C satisfying
CV/2I greater than 2tCK
represents the maximum value C max meeting the I/2 component of the phase difference T:
C max=4tCKxc2x7I/Vt.
In the case of the different phase input, the N-channel MOS transistor MN1 is turned on by the rising of the input signal IN1 from the low level to the high level to discharge the electrical charges at the current I. After T=tCK, the N-channel transistor MN2 is turned on by the rising of the input signal IN2 from the low level to the high level.
If the electrical charges of the node N26, that need to be extracted until the threshold value of the inverter INV3 is reached, are CV, and the current with which the electrical charges of the N-channel MOS transistors MN1 and MN2 is I, respectively, the electrical charges CV are extracted with the current I during the phase difference T as from the rising of the first input signal IN1 until the rising of the second input signal IN2 and thereafter with the current 2I.
If the electrical charges CV are extracted during the phase difference T until the rising of the second input signal IN2, the I/2 component of the phase difference T is removed. So,
CV/I less than T
and
C min=tCKxc2x7I/Vt.
The period of extraction with the current 2I is the overlap period Tovp of the first input signal IN1 and the second input signal IN2. If the CV is not completely extracted during this overlap period Tovp, the output of the timing difference division circuit is devoid of the I/2 component of the phase difference T.
So, the maximum capacitance value C which satisfies
xe2x80x83(CVxe2x88x92Txc2x7I)/2I less than T
represents the maximum value C max:
C max=(2Txc2x7+T)I/V=3tCKxc2x7I/Vt
which satisfies the I/2 component (T/2) of the phase difference T.
If two four-phase clock signals, with a period tCK, are input, to output a signal with a delay just equal to xc2xd (2tCK), the ratio of the minimum value C min to the maximum value C max of the value of the capacitance appended to the inner node N26 subjected to charging/discharging is approximately 1:3, as shown in FIG. 28, in which the ordinate is the ratio of the interior division of the timing difference division circuit (dividing ratio), which, from the delay time of A1 to A3 in FIG. 27b, is equivalent to A2/(A3xe2x88x92A2), and the abscissa is the value of the capacitance appended to the interior node N26.
In the structure of the conventional timing difference division circuit, shown in, for example, FIG. 26 etc., the MOS transistors and the MOS capacitance are used to adjust the value of the capacitance of the capacitance device CAP appended to the inner node, there is required an area corresponding to the area of the MOS transistors and the MOS capacitances, thus increasing the chip area.
It is therefore an object of the present invention to provide a timing difference division circuit and a method for timing difference division whereby the operating speed may be increased and the chip area may be prevented from being increased while enabling a broadband operation.
According to a first aspect of the present invention, there is provided a timing difference division circuit (e.g., interpolator) at least comprising:
two switches connected in parallel to control a path between an inner node and a power source on or off, one of switches being turned on based on one of two input signals undergoing faster transition to charge or discharge a capacitance appended to the inner node with a first current, the other switch being turned on based on the other input signal undergoing transition with a delay with respect to the one input signal, capacitance appended to the inner node being charged or discharged through the one switch in the on-state and the other switch in the on-state with a current value corresponding to a sum of the first current and a second current;
there being provided a buffer circuit an output logic value of which is changed when the voltage of the inner node exceeds or is smaller than a threshold value. The timing difference division circuit further comprises a circuit unit for setting, based on the one signal and on the other signal, an overlap period (Tovp) during which an on time period of the one switch is overlapped with an on time period of the other switch, to a desired value.
According to a second aspect of the present invention, the aforementioned circuit unit elongates the overlap period (Tovp) forwardly of a leading edge of the other signal undergoing transition with a delay from the one signal. The overlap period (Tovp) may also begin at the leading edge of the other signal and may be further extended from the trailing edge of the one signal so that the overlap period will have an optionally selected value.
According to a third aspect of the present invention, the circuit unit sets the overlap period Tovp so that it begins at the forward edge of the other signal undergoing transition with a delay from the one signal and ends at the trailing edge of the other signal.
According to a fourth aspect of the present invention, the capacitance of the inner node is made up of plural capacitances (typically of MOS capacitors), the connection of which to the inner node is controlled by a control signal.
According to a fifth aspect, there is provided a timing difference division circuit comprising:
a logic circuit generating and outputting a first gate signal and a second gate signal based on a first input signal; and
a first switch element connected across a first power source and an inner node and having a control terminal to which is fed the first gate signal;
a first series circuit made up of a second switch element and a first constant current source and a second series circuit made up of a third switch element and a second constant current source, the first and second series circuits being connected in parallel across the inner node and the second power source;
the first and second gate signals being connected to control terminals of the second and third switches, respectively;
the timing difference division circuit further comprising:
a plurality of MOS capacitors, connection of which to the inner node being separately controlled by a control signal; and
a buffer circuit an input end of which is connected to the inner node and the value of an output signal of which is determined based on the relative magnitude of a potential of the inner node and a threshold voltage;
wherein an overlap period during which the first and second gate signals output from the logic circuit are both activated to turn on the second and third switch elements is set to an optional value.
According to a sixth aspect, there is provided a timing difference division circuit comprising:
a logic circuit generating and outputting a first gate signal and a second gate signal based on a first input signal and a second input signal;
a first MOS transistor of a first conductivity type, having a source, a drain and a gate connected to a first power source, an inner node and to the first gate signal, respectively;
second and third MOS transistors of a second conductivity type having drains commonly connected to the inner node and to the gates of which the first and second gate signals are connected;
a first constant current source and a second constant current source connected across a source of the second MOS transistor and the second power source and across a source of the third MOS transistor and the second power source, respectively;
a plurality of MOS transistors of the first conductivity type, having sources and drains connected to the inner node and to the gates of which control signals are connected; and
a buffer circuit an input end of which is connected to the inner node and the value of an output signal of which is determined based on the relative magnitude of the potential of the inner node and a threshold voltage;
wherein an overlap period during which the first and second gate signals output from the logic circuit are both activated to turn on the second and third MOS transistors simultaneously is set to an optional value.
In the timing difference division circuit of the fifth or sixth aspect, the following may be employed.
The logic circuit outputs, as the first gate signal, a signal the timing of a beginning edge of which is determined by a beginning edge of one of the first and second input signals having a leading phase and the timing of an end edge of which is determined by an end edge of the input signal having a lagging phase;
the logic circuit outputting, as the second gate signal, a signal the timing of a beginning edge of which is determined by a beginning edge of one of the first and second input signals having a lagging phase and the timing of an end edge of which is determined by an end edge of the input signal having the lagging phase.
Also, the following structure may be employed:
The logic circuit includes a first gate circuit outputting a first value as the first gate signal when the first and second signals assume first and second values, respectively, or both assume the second value such that both of the first and second signals assume values other than the first value; and
a second gate circuit outputting a first value as the second gate signal when the signal of the lagging phase assumes a second value.
Further, the following structure may be employed:
The logic circuit outputs, as the first and second gate signals, an in-phase signal the timing of a beginning edge of which is determined by a beginning edge of one of the first and second input signals having a leading phase and the timing of an end edge of which is determined by an end edge of the input signal having a lagging phase.
The capacitance values of plural MOS capacitors are connected to the inner node differ from one another.
For the fourth or fifth aspect, the plural MOS transistors of the first conductivity type, the sources and drains of which are connected to the inner node, may be of respectively different gate lengths or gate widths.
For the sixth aspect, the first and second input signals may be made up of clocks of respectively different phases generated on frequency division of input clock signals; and
the control signal fed to the gates of the plural MOS transistors of the first conductivity type, the sources and drains of which are both connected to the inner node, is supplied from a circuit detecting the period of the clocks.
According to a seventh aspect, there is provided a clock controlling circuit for generating and outputting multi-phase clocks on frequency division of input clocks;
the clock controlling circuit comprising:
a frequency divider generating and outputting multi-phase clocks by frequency-dividing an input clock;
a period detection circuit for detecting the period of the input clock; and
a multi-phase multiplying circuit being fed as input with multi-phase clocks output from the frequency divider to generate multi-phase clocks multiplied from the clocks;
wherein the multi-phase multiplying circuit includes:
a plurality of timing difference division circuits outputting a signal corresponding to division of the timing difference of two inputs as defined in any one of first to sixth aspects, and
a plurality of multiplexing circuits multiplexing and outputting outputs of two of the timing difference division circuits.
The clock controlling circuit may further comprise a two-phase clock multiplying circuit, wherein the two-phase clock multiplying circuit includes:
four timing difference division circuits being fed with two-phase clocks and outputting a signal corresponding to division of the timing difference of two inputs, and
two multiplexing circuits one being fed with outputs of the first and third timing difference division circuits and the other being fed with outputs of the second and fourth timing difference division circuits.
For the clock controlling circuit,
the multi-phase clock multiplying circuit may include
(a) 2n timing difference division circuits each being fed with n-phase clocks (first to nth clocks) and outputting a signal corresponding to the division of the timing difference of two inputs;
the 2Ixe2x88x921st timing difference division circuit, where 1xe2x89xa6Ixe2x89xa6n, being fed with the same Ith clock as the two inputs;
the 2Ith timing difference division circuit, where 1xe2x89xa6Ixe2x89xa6n, being fed with the Ith clock and (I+1 mod n)th clock, as inputs, where xe2x80x9cmodxe2x80x9d denotes remainder processing and I+1 mod n means a remainder resulting from division of I+1 by n;
(b) 2n pulse width correction circuits fed with an output of the Jth timing difference division circuit, where 1xe2x89xa6Jxe2x89xa62n, and with an output of the (J+2mod n) th timing difference division circuit, where n is a remainder obtained on dividing J+2 with n, as inputs; and
(c) n multiplexing circuits fed each with an output of the Kth pulse width correction circuit, where 1xe2x89xa6Kxe2x89xa6n, and with an output of the (K+n)th pulse width correction circuit, as inputs.
According to an eighth aspect, there is provided a signal controlling method in which one of two switches connected in parallel across an inner node and a power source is turned on based on one of two input signals undergoing faster transition to charge or discharge a capacitance of the inner node with a first current,
the other switch being turned on based on the other input signal undergoing transition with a delay with respect to the one input signal, the capacitance of the inner node being charged or discharged through the one switch in the on-state and the other switch in the on-state with a current value corresponding to a sum of the first current and a second current, an output logic value of the buffer circuit being changed when the voltage of the inner node exceeds or is smaller than a threshold value of the buffer circuit to output from the buffer circuit a signal of a delay time corresponding to a divided value of the timing difference of two input signals;
wherein based on the one signal and the other signal, an overlap period (Tovp) during which an on time period of the one switch is overlapped with an on time period of the other switch is made adjustable to a desired value to enlarge the range of the capacitance appended to the inner node with respect to the divided value of the timing difference of the two input timing signals.
In the signal controlling method,
the overlap period (Tovp) may be elongated forwardly of a leading edge of the other signal undergoing transition with a delay with respect to the one signal or the overlap period (Tovp) is caused to begin at the leading edge of the other signal and to be elongated rearwardly of the trailing edge of the one signal so that the overlap period will have an optional value.
In the signal controlling method, the overlap period (Tovp) may be caused to begin at the forward edge of the other signal undergoing transition with a delay from the one signal and to end at the trailing edge of the other signal.
According to a ninth aspect, there is provided a signal controlling method in which first and second input signals with respective different phases are input and an output signal of a delay time determined by a time resulting from division of a timing difference between the two input signals,
wherein from the first and second input signals, a first gate signal and a second gate signal are generated,
the timing of a beginning edge of the first gate signal being determined based on a beginning edge of one of the first and second input signals having a leading phase, and the timing of an end edge of the first gate signal being determined by an end edge of the input signal having a lagging phase, and
the timing of a beginning edge of the second gate signal being determined by a beginning edge of one of the first and second input signals having a lagging phase, and the timing of an end edge of the second gate signal being determined by an end edge of the input signal having the lagging phase,
the capacitance of the inner node is first charged or discharged by one of first and second switch elements connected across the inner node and a power source, the one being turned on based on the first gate signal;
subsequently the capacitance of the inner node is also charged or discharged by the switch element turned on based on the second gate signal in conjunction with the switch element turned on based on the second gate signal; and
wherein from a buffer circuit to an input end of which the inner node is connected and an output logic value of which is changed in case where the inner node voltage exceeds or is smaller than a threshold value, an output signal including a time resulting from division of the timing difference of the first and second input signals is output.